library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--use ieee.std_logic_arith.all;

entity k_Unit is
	
	generic ( Z : positive range 1 to 256 ) ;
	
	port (
		p : in  std_logic_vector(Z-1 downto 0);
		S : out std_logic_vector(Z-1 downto 0)
	);
end entity;

------------------------------------------------------------------------------

architecture k_Unit1 of k_Unit is
	signal k : std_logic_vector(Z-1 downto 0)  ;
        --signal i : unsigned(Z-1 downto 0)  ;
	
begin  -- k_Unit1
	process (p)
		begin  -- process
--		S <= (others => '0') ;
		for i in Z-1 downto 0 loop
			if p(i) = '1' then
				S <= std_logic_vector(to_unsigned(i,Z));
				exit;
                        else
                          S <= (others => '0');
			end if;
		end loop;  -- i
	end process;
end k_Unit1;

